Integrated circuit company Montage Technology has launched its CXL 3.1 Memory eXpander Controller (MXC), which is currently being tested by some of its key customers, including AMD and Intel. The controller is compliant with the CXL 3.1 Type 3 specification – the latest version of the CXL interconnect standard – and supports CXL.mem and CXL.io protocols. Montage Technology says it delivers low-latency memory expansion, high-bandwidth performance, and polling suitable for next-gen data centre servers.
The CXL 3.1 MXC is built on a PCIe 6.2 physical layer interface and can achieve data transfer rates of 64 GT/s (x8). It offers flexible configuration with multi-width and multi-rate support, allowing it to be split via two x4 ports. It measures 25 mm x 25 mm, and supports EDSFF (E3.S) and PCIe add-in card (AIC) form factors common in high-performance computing environments; servers, all-flash arrays, and edge computing platforms. The chip has a dual-channel DDR5 memory controller that can operate at speeds of up to 8000 MT/s (million transfers per second).
The controller includes dual RISC-V microprocessors acting as an Application Processing Unit (APU) and Security Processing Unit (SPU) to support system management. The system can adjust DDR and CXL memory resources on the fly, manage security in-hardware, and respond to system events in real-time.
Multiple communication interfaces are also featured, including SMBus/I3C – for sensor and control data, SPI – for high-speed communication with other chips, and JTAG – used to test and debug hardware. The chip can perform firmware updates without complex processes.
Raghu Nambiar, Corporate Vice President, Data Center Ecosystems and Solutions at AMD, said, “CXL Memory expansion and tiering is a foundational technology for the future of data centre computing, especially in enabling heterogeneous memory architectures.”
Intel’s Ronak Singhal said the CXL 3.1 MXC is a “meaningful step toward scalable memory architectures and an expanded CXL ecosystem.”
With the demand for cloud resource pooling increasing, standard memory architectures can experience scalability and bandwidth bottlenecks. With CXL memory pooling, Montage Technology aims to help customers use memory more effectively.
Stephen Tai, President at Montage Technology, said the CXL 3.1 MXC “accelerates the industry’s adoption of disaggregated memory architectures through standards-based solutions, [as a] foundation for memory pooling and sharing in next-generation computing infrastructure.”
(Image source: “chip” by osde8info is licensed under CC BY-SA 2.0.)
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